Prior to fabrication or manufacturing, integrated circuit devices generally undergo a series of computer simulations to ensure proper functionality of the device. These simulations generally include logic simulations to ensure the device functions as expected and power simulations to ensure the device consumes the expected amount of power during use. To perform these simulations, a simulator may apply a series of input vectors or patterns to a gate-level logic netlist that represents the integrated circuit design. The simulator will then monitor the transitions of the gates of the integrated circuit as the patterns propagate through the circuit.
Logic simulations using commercial simulators are typically event driven, meaning that the simulator does not need to compute the state for each gate at every clock cycle. Instead, the simulator may only note the output of a gate when the input to the gate has changed. This makes commercial simulators very fast at performing logic simulations with long input vectors since, typically at any one time, only a small subset of gates in a netlist see value changes on their inputs during simulation.
Conversely, power simulations of complex integrated circuits are not event driven. Many power simulators use a logic simulation as described above to monitor gates as they change states to predict the power consumption for each state change. However, power simulators must also monitor each gate that is not changing to account for current that may leak from the gate at every clock cycle. The combination of power consumed during the state changing of the gates and the amount of current leak of the non-changing gates give an overall picture of power consumption.